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Semiconductor MSM5117405B
Semiconductor
MSM5117405B
E2G0039-17-41
4,194,304-Word 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM5117405B is a 4,194,304-word 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5117405B achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5117405B is available in a 26/24-pin plastic SOJ or 26/24-pin plastic TSOP.
FEATURES
* 4,194,304-word 4-bit configuration * Single 5 V power supply, 10% tolerance * Input : TTL compatible, low input capacitance * Output : TTL compatible, 3-state * Refresh : 2048 cycles/32 ms * Fast page mode with EDO, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * Multi-bit test mode capability * Package options: 26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM5117405B-xxSJ) 26/24-pin 300 mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM5117405B-xxTS-K) (TSOPII26/24-P-300-1.27-L) (Product : MSM5117405B-xxTS-L) xx indicates speed rank.
PRODUCT FAMILY
Family MSM5117405B-50 MSM5117405B-60 MSM5117405B-70 Access Time (Max.) tRAC tAA tCAC tOEA 50 ns 25 ns 13 ns 13 ns 60 ns 30 ns 15 ns 15 ns 70 ns 35 ns 20 ns 20 ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 90 ns 110 ns 130 ns 660 mW 605 mW 550 mW 5.5 mW
231
MSM5117405B
PIN CONFIGURATION (TOP VIEW)
VCC 1 DQ1 2 DQ2 3 WE 4 RAS 5 NC 6 A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13 26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE 21 A9 19 A8 18 A7 17 A6 16 A5 15 A4 14 VSS VCC 1 DQ1 2 DQ2 3 WE 4 RAS 5 NC 6 A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13
,
26 VSS 25 DQ4 23 CAS 22 OE 24 DQ3 21 A9 19 A8 18 A7 17 A6 16 A5 15 A4 14 VSS Function Address Input Row Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5 V) Ground (0 V) No Connection
Semiconductor
VSS 26
1 VCC 2 DQ1 3 DQ2 4 WE 5 RAS 6 NC 8 A10 9 A0 10 A1 11 A2 12 A3 13 VCC
DQ4 25 CAS 23 OE 22 A9 21 A8 19 A7 18 A6 17 A5 16 A4 15 VSS 14
DQ3 24
26/24-Pin Plastic SOJ
26/24-Pin Plastic TSOP (K Type)
26/24-Pin Plastic TSOP (L Type)
Pin Name A0 - A10 RAS CAS DQ1 - DQ4 OE WE VCC VSS NC
Column Address Strobe
Note :
The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.
232
Semiconductor
MSM5117405B
BLOCK DIAGRAM
Timing Generator Timing Generator
RAS CAS
11
Column Address Buffers
11
Column Decoders
Write Clock Generator
WE OE
4
A0 - A10
Internal Address Counter
Output Buffers
4 4
Refresh Control Clock
Sense Amplifiers
4
I/O Selector
4 4
DQ1 - DQ4
Input Buffers
4
11
Row Address Buffers
11
Row Decoders
Word Drivers
Memory Cells
VCC On Chip VBB Generator On Chip IVCC Generator VSS
233
MSM5117405B
Semiconductor
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD* Topr Tstg Rating -0.5 to VCC + 0.5 -0.5 to 7 50 1 0 to 70 -55 to 150 Unit V V mA W C C
*: Ta = 25C Recommended Operating Conditions
(Ta = 0C to 70C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -0.5*2 Typ. 5.0 0 -- -- Max. 5.5 0 VCC + 0.5*1 0.8 Unit V V V V
Notes : *1. The input voltage is VCC + 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VSS is applied). Capacitance
(VCC = 5 V 10%, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (A0 - A10) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ4) Symbol CIN1 CIN2 CI/O Typ. -- -- -- Max. 5 7 7 Unit pF pF pF
234
Semiconductor DC Characteristics
Parameter Output High Voltage Output Low Voltage Input Leakage Current Condition
MSM5117405B
(VCC = 5 V 10%, Ta = 0C to 70C)
Symbol
MSM5117405 MSM5117405 MSM5117405 B-50 B-60 B-70 Unit Note Min. Max. VCC 0.4 10 Min. 2.4 0 -10 Max. VCC 0.4 10 Min. 2.4 0 -10 Max. VCC 0.4 10 V V mA 2.4 0 -10
VOH IOH = -5.0 mA VOL IOL = 4.2 mA 0 V VI 6.5 V; ILI All other pins not under test = 0 V DQ disable 0 V VO 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH RAS, CAS VCC -0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min.
Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode)
ILO
-10
10
-10
10
-10
10
mA
ICC1
-- -- --
120 2 1
-- -- --
110 2 1
-- -- --
100 2
mA
1, 2
ICC2
mA 1
1
--
120
--
110
--
100
mA
1, 2
--
5
--
5
--
5
mA
1
--
120
--
110
--
100
mA
1, 2
--
110
--
100
--
90
mA
1, 3
Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH.
235
MSM5117405B AC Characteristics (1/2)
Semiconductor
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3, 12, 13 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Data Output Hold After CAS Low CAS to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode with EDO) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time
Symbol
MSM5117405 MSM5117405 MSM5117405 B-60 B-50 B-70 Unit Note Min. Max. -- -- -- -- 50 13 25 30 13 -- -- 13 13 13 13 50 32 -- 10,000
100,000
Min. 104 135 25 68 -- -- -- -- -- 0 5 0 0 0 0 1 -- 40 60 60 10 10 10 10 40 5 35 5 14 12 0 10 0 10 30
Max. -- -- -- -- 60 15 30 35 15 -- -- 15 15 15 15 50 32 -- 10,000
100,000
Min. 124 160 30 78 -- -- -- -- -- 0 5 0 0 0 0 1 -- 50 70 70 13 13 10 13 45 5 40 5 14 12 0 13 0 13 35
Max. -- -- -- -- 70 20 35 40 20 -- -- 20 20 20 20 50 32 -- 10,000
100,000
tRC tRWC tHPC tHPRWC tRAC tCAC tAA tCPA tOEA tCLZ tDOH tCEZ tREZ tOEZ tWEZ tT tREF tRP tRAS tRSH tROH tCP tCAS tCSH tCRP tRHCP tCHO tRCD tRAD tASR tRAH tASC tCAH tRAL
84 110 20 58 -- -- -- -- -- 0 5 0 0 0 0 1 -- 30 50 50 7 7 7 7 35 5 30 5 11 9 0 7 0 7 25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 7, 8 7, 8 7 7 3 4, 5, 6 4, 5 4, 6 4 4 4
RAS Pulse Width (Fast Page Mode with EDO) tRASP
-- -- -- 10,000 -- -- -- -- 37 25 -- -- -- -- --
-- -- -- 10,000 -- -- -- -- 45 30 -- -- -- -- --
-- -- -- 10,000 -- -- -- -- 50 35 -- -- -- -- --
236
Semiconductor AC Characteristics (2/2)
MSM5117405B
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3, 12, 13 Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode)
Symbol
MSM5117405 MSM5117405 MSM5117405 B-50 B-60 B-70 Unit Note Min. Max. Min. 0 0 0 0 10 10 10 10 10 10 10 10 0 10 15 34 49 79 54 5 5 10 10 10 10 10 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0 0 0 0 13 10 10 13 10 10 13 13 0 13 20 44 59 94 64 5 5 10 10 10 10 10 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 10 10 10 10 9 9 10 0 0 0 0 7 7 7 7 7 7 7 7 0 7 13 30 42 67 47 5 5 10 10 10 10 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tRCS tRCH tRRH tWCS tWCH tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH
237
MSM5117405B Notes:
Semiconductor
1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test mode CA0 and CA1 are not used and each DQ pin now accesses 4-bit locations. Since all 4 DQ pins are used, a total of 16 data bits can be written in parallel into the memory array. In a read cycle, if 4 data bits are equal, the DQ pin will indicate a high level. If the 4 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.
See ADDENDUM M for AC Timing Waveforms
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